MohammadHossein AskariHemmat
Research
My main area of research is making Deep Neural Networks more computationally efficient. I approach this problem by proposing new algorithms and custom hardwares.
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RISC-V Barrel Processor for Deep Neural Network Acceleration
ISCAS 2021
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Based on the architecture proposed in our FCCM 2020 paper, we built a RISC-V core that is connected to a neural network accelerator capable of performing Matrix Vector product. We used this system to compute a GEMV operation with an input matrix size of 8 by 128 and a weight matrix size of 128 by 128 with two-bit precision in only 16 clock cycles.
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RISC-V Barrel Processor for Accelerator Control
FCCM 2020
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In this paper we designed a Barrel RISC-V processor. We used 8 harts (hardware threads) to control 8 Matrix Vector Units for a Deep Neural Network application. We have implemented our design on a Xilinx Ultrascale FPGA. Our 8-hart barrel processor runs at 350 MHz with CPI of 1 and consumes 0.287W.
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Talks/Workshops
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Hardware Aware Acceleration For Deep Neural Network
CMC Workshop: Accelerating AI - Challenges and Opportunities in Cloud and Edge Computing, Mar 6th, 2020
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In this presentation, I talked about how to accelerate computation in Deep Neural Networks. Specifically, I talked about Quantization. Quantization in Deep Learning is a technique to reduce power, memory and computation time of deep neural networks. I talked about how one can improve the performance of a DNN using both software and hardware solutions.
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Workshop on New Methods on Designing Digital Systems
CMC Workshop: Accelerating AI - Challenges and Opportunities in Cloud and Edge Computing, Mar 6th, 2020
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In this workshop, I reviewed the most popular open source tools for design and simulation of digital systems. The attendants got a chance to use these tools and developed a simple circuit to calculate GCD. In the second part of the workshop, I talked about RISC-V and Chisel. At the end of the workshop, the attendants got a chance to use chisel to designa and simulate a 3-stage pipelined RISC-V core.
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